Silicon University collaborated with Sevya Multimedia and the VLSI Society of India (VSI) to host the VLSI Summit on Nanotechnology and Embedded Systems (NES) 2024-25 from 31 January to 1 February 2025.
The objective of NES 2025 was to create awareness about the recent advances in solid-state devices, VLSI circuits, and embedded systems. The workshop featured expert talks and hands-on training sessions led by eminent speakers from top semiconductor companies. Its primary goal was to equip participants with advanced skills, while also providing valuable networking opportunities with industry leaders in VLSI and embedded systems. This allowed attendees to enhance their expertise and explore potential career paths in these cutting-edge technologies.
The inauguration ceremony was graced by Shri Manas Panda, Special Secretary, Electronics and Information Technology Department, Government of Odisha, Mr. Steve Hoover, Founder of Redwood EDA, Mr. Mrinal Das, Head of PVT Sensor IP at Synopsys, Dr. Ajit Kumar Panda, Vice President (Engineering RF) at VVDN Technologies, and Mr. Narasayya Donepudi of Sevya Multimedia. The technical sessions featured expert speakers who shared their deep insights into the evolving landscape of VLSI. Dr. Satya Gupta, President of the VLSI Society of India (VSI), Mr. Atul Bhargava, Senior Group Manager and Senior Member Technical Staff at STMicroelectronics, Noida, Dr. Shivananda Koteshwar, Managing Director and India Site Head at Astera Labs, Mr. Rama Krishna Dorairaju, Distinguished Engineer and Senior Director at Astera Labs, USA, and Mr. Puneet Mittal, Founder of VLSI Expert, addressed the audience, shedding light on the latest trends, innovations, and emerging opportunities in the VLSI domain.
A highlight of the event was an engaging panel discussion on the impact of Artificial Intelligence in analog VLSI design. The session, moderated by Mr. Atul Bhargava, sparked insightful conversations and provided valuable perspectives on the integration of AI in VLSI.
The second day of NES 2025 featured an interactive workshop on the ‘RTL-to-GDS flow utilizing the Synopsys Inc Toolchain’, organized as a pivotal part of the Chip-to-Startup (C2S) Program. Led by Mr. Puneet Mittal, Founder of VLSI Expert, the workshop provided a comprehensive exploration of the RTL-to-GDSII process, bridging theoretical concepts with practical applications in chip design. The session drew an enthusiastic and diverse group of over forty participants, including faculty members, students, and professional engineers, all eager to gain hands-on experience and valuable insights into this critical stage of semiconductor development. The interactive nature of the workshop allowed participants to engage deeply with the material, enhancing their understanding of the complete design flow from the Register Transfer Level (RTL) to the final GDSII layout.
NES 2025 successfully bridged the gap between academia and industry, offering participants invaluable insights into the evolving fields of VLSI, nanotechnology, and embedded systems. Through expert talks, hands-on workshops, and engaging discussions, the summit empowered attendees with advanced skills and inspired future innovations in semiconductor design.
