Advanced VLSI Lab

VLSI Course for New College Graduates (NCGs)

New College Graduates (NCGs) have been trained in the three major VLSI domains of Process Design Kit (PDK) development, DRAM Memory verification, and Custom Layout Design.

The objective was to accelerate the training of New College Graduates (NCGs) so that they can be placed in industry projects immediately after completing 2-3 months of training. Prior to this training (part of our Launch Lab initiative), the typical requirement by the VLSI industry was 2-3 years of experience for NCGs.

38 NCGs from 20 different colleges in India and abroad including Queen’s University Belfast UK, IIT Kharagpur, NIT Warangal, NIT Allahabad, NIT Jaipur, NIT Jamshedpur, BIT Mesra and BIT Sindri have completed this training.

After completion of this training,

• A total of 15 trainees have been placed on direct client projects at two leading semiconductor companies through Sevya Multimedia.
• 10 SiliconTech students were directly hired by six leading semiconductor companies viz., Mentor Graphics, Micron Technology, Synopsys, Intel, Wipro VLSI and HCL VLSI

Analog and Mixed-signal VLSI Design, Characterization and Layout

Analog and mixed-signal (AMS) VLSI design, a highly important domain in the VLSI industry, is characterised by design complexity, competitive specifications, technology dependency, and full custom design.

This course will help participants develop sound knowledge on AMS VLSI design through theory and practice sessions on analog devices, circuits, and circuit design. They will gain experience in circuit characterisation and layout design. All the laboratory projects will be done using commercial EDA tools (Cadence) and 0.18um HV SOI process technology for design and layout.

After completion of this course, the participants will able to:

• understand the biasing of the circuits, small-signal model and large-signal behaviors of MOSFETS, and frequency response of the circuits
• design and characterise simple circuits, design layouts of different circuits considering layout rules, and frame recommendations and guidelines
• design current mirrors, error amplifiers, comparators, sample-and-hold circuits, etc
• floor plan, placement, and routing of highly complex blocks like bandgap reference (BGR), digital-to-analog converter (DAC), temperature sensor circuits, oscillators, etc

Pcell development using SKILL Scripting

Scripting is a necessity for CAD engineers but can also enable circuit designers to do complex activities efficiently. SKILL programming language lets designers quickly and easily customise existing CAD applications and develop new applications.

Based on the artificial intelligence language Lisp, SKILL scripting language can be used to develop a parameterised cell, or PCell. It is a programmable cell that lets designers create a customised instance each time they place it.

This course aims to develop Pcells using SKILL scripting in 0.18um CMOS technology.

After this training, the participants will be able to:

• create Pcells using SKILL scripting
• add labels to pins in a layout
• generate layout from schematic view from all cells in a library
• create rectangular and polygon shape with specific width and length
• create a CDF information for the Pcell

Digital VLSI Design Course and Laboratory for Undergraduate Students

This course is specifically designed for undergraduate students to understand, design, and characterize combinational and sequential circuits, dynamic logic circuits, and different types of memory circuits.

Students will learn about MOS Structure and MOSFET operations, Inverter design, dynamic circuits (DOMINO, NORA, ZIPPER, TSPC) design, and memory design (SRAM, DRAM). Laboratory experiments will help them better understand the application of combinational and sequential design topics.

At the end of the course, students will develop a thorough understanding of:

• MOSFET and its operations for digital logic design
• static (VTC, Noise Margin) and dynamic characteristics (Delay, power) which will help design and characterize any type of digital logic
• design and timing characterization (setup time, hold time, recover time, removal time) of sequential circuits (Latch, D-FF)
• design of high-performance dynamic logic circuits (DOMINO, NORA, ZIPPER, TSPC, etc)
• design of static random access memory (SRAM) circuits

Foundation of VLSI for undergraduate, postgraduate and industry freshers

This summer course is designed to provide good fundamentals as well as engineering knowledge in the VLSI domain. It has lessons on MOSFET operation, combinational circuit designs, and sequential logic design, to the highly complex Static Timing Analysis (STA), Logic Synthesis (LS), and Physical Design (PD). The final part of this course ends with a hands-on session using OpenSTA.

The expected course outcomes are to:

• provide strong fundamentals on CMOS technology, MOSFET operations, combinational and sequential designs
• provide a detailed understanding of backend digital design as well as standard cell library and its use
• provides detailed knowledge on basic and advanced static timing analysis of digital VLSI design
• give hands-on training facility through OpenSTA to check different timing characteristics of a complex design

CMOS VLSI Design

This summer course was designed to provide adequate theoretical and domain knowledge for undergraduate students to design, simulate, layout, and test a Serial Peripheral Interface (SPI) for a 32-byte Static Random Access Memory (SRAM) using a 0.6um CMOS Technology.

At the end of the course, students will be able to:

• understanding SPI and SRAM and their interfacing
• design and layout the shift register, SPI controller, 5-bit counter, comparator using commercial EDA tool (Tanner)
• design a 5-bit address latch and read-write latch using the commercial EDA tool (Tanner)
• design synchronous circuit for signal generation using commercial EDA tool (Tanner)
• learn verification (DRC, LVS) and parasitic extraction (PEX) of SPI using a commercial verification tool (Mentor Graphics)
• understand the test setup and silicon testing

Analog Integrated Circuits: Analysis, Design and Layout

This course will provide a strong analytic foundation in circuits, systems, and CMOS design allowing the participants to tackle complex industry challenges in various Deep Sub-micron Technology processes.

Laboratory exercises and projects are based on industry IP blocks using commercial full-custom EDA toolchain from cadence design systems, providing the participant with an entire backend experience (design abstraction to chip fabrication).

Two commercial sub-micron CMOS semiconductor technologies, 0.18um SOI HV and 0.6um CMOS are used for the design and layout of the circuit. In the laboratory, current mirrors, differential amplifier, source follower, and other essential components required for the project are designed.

From this training, the participants will be able to:

• learn Linux and Python basics, circuit and system basics, CMOS process, basics of analog circuit design, full custom design, etc.
• understand the analog integrated circuit design flow
• understand and design the basic analog IC components like current mirrors, single-stage amplifiers, and differential amplifiers
• understand the frequency response and feedback analysis
• design and layout of a standard low-power and low-noise bandgap reference (BGR) circuit
• fully characterize the BGR circuits